1. Technical Field
This invention relates to clock circuits, and has particular relation to circuits for producing an output clock signal (preferably in-phase and quadrature) which is one-third the frequency of an input clock signal.
2. Background Art
Modern digital equipment is clocked at increasingly fast speeds. At the same time, it is often necessary to clock some equipment at a clock frequency which is only a third of the frequency of an available signal. Three is not a power of two, and most digital architecture involves powers of two, so this is not a trivial exercise.
The following United States patents have addressed divide-by-three circuits:
An apparatus is disclosed which provides divide-by-three capabilities using only two data flip-flops (DFFs), a NOR gate, and an OR gate. If the input clock signal is bi-phase (both in-phase and quadrature), bi-phase capabilities can be added with only two more DFFs and one more OR gate.
In its broadest aspect, an in-phase divide-by-three circuit comprises:
(a) a first data flip-flop (DFF) connected to receive, at a clock input, an in-phase input clock signal having an input frequency;
(b) a second DFF connected to receive:
(1) at a clock input, the in-phase input clock signal; and
(2) at a data input, a slave output from the first DFF;
(c) a NOR gate, connected:
(1) to receive:
(A) the slave output signal from the first DFF; and
(B) a slave output signal from the second DFF; and
(2) to apply a NOR output signal to a data input of the first DPF; and
(d) an OR gate, connected to receive:
(1) the slave output signal from the first DFF; and
(2) a master output signal from the second DFF;
whereby an output of the in-phase OR gate produces an output in-phase clock signal having an output frequency equal to one third of the input frequency.